VLSI CAD Part II: Layout
Learn key VLSI CAD tools for ASIC/SoC design. Focus on logic-to-layout mapping, placement, routing, and timing analysis.
Learn key VLSI CAD tools for ASIC/SoC design. Focus on logic-to-layout mapping, placement, routing, and timing analysis.
This course, VLSI CAD Part II: Layout, is an in-depth exploration of the computer-aided design (CAD) tools used in creating Application Specific Integrated Circuits (ASIC) and System on Chip (SoC) designs. It focuses on the crucial steps of transforming logic designs into physical layouts. Students will learn about technology mapping, ASIC placement and routing, and timing analysis. The course covers fundamental algorithms and data structures used in these tools, aiming to provide a deep understanding of how they function. Key topics include iterative and analytical placement methods, maze routing techniques, and static timing analysis. This course builds on VLSI CAD Part I: Logic and prepares students to understand and work with advanced VLSI design tools and methodologies.
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پښتو, বাংলা, اردو, 2 more
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What you'll learn
Understand the ASIC layout process and the role of technology libraries
Master technology mapping techniques for translating logical designs into real gates
Learn both iterative and analytical placement algorithms for efficient gate positioning
Explore maze routing techniques for connecting placed components
Understand static timing analysis for evaluating design performance
Gain practical experience through programming assignments in placement and routing
Skills you'll gain
This course includes:
580 Minutes PreRecorded video
7 quizzes, 2 programming assignments
Access on Mobile, Tablet, Desktop
FullTime access
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There are 6 modules in this course
This course dives deep into the VLSI CAD tools essential for ASIC and SoC design, focusing on the critical steps from logic to layout. Students will explore technology mapping, which translates synthesis output into real logic gates. The course covers both iterative and analytical placement algorithms, teaching students how to efficiently position millions of gates on a chip. Routing techniques, particularly maze routing, are examined in detail, showing how to connect the placed components. The course concludes with an in-depth look at static timing analysis, enabling students to evaluate the speed and performance of their designs. Throughout, the emphasis is on understanding the fundamental algorithms and data structures that power these sophisticated CAD tools.
Orientation
Module 1 · 1 Hours to complete
ASIC Placement
Module 2 · 3 Hours to complete
Technology Mapping
Module 3 · 6 Hours to complete
ASIC Routing
Module 4 · 3 Hours to complete
Timing Analysis
Module 5 · 6 Hours to complete
Final Exam
Module 6 · 3 Hours to complete
Fee Structure
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Instructor
Pioneering Innovator in Integrated Circuit Design
Rob A. Rutenbar is an Adjunct Professor of Computer Science at the University of Illinois at Urbana-Champaign, where he has made significant contributions to the field of integrated circuit design over his extensive career. He earned his Ph.D. from the University of Michigan in 1984 and spent 25 years on the faculty at Carnegie Mellon University before joining Illinois in 2010 as the Head of the Computer Science Department. His research focuses on design tools for integrated circuits, encompassing synthesis, optimization, formal verification, simulation, and geometric layout. Rutenbar co-founded Neolinear Inc. to commercialize innovative analog circuit design tools and served as Chief Scientist until its acquisition by Cadence in 2004. His expertise has earned him numerous accolades, including being named a Fellow of both the IEEE and ACM, and receiving prestigious awards such as the Semiconductor Research Corporation Aristotle Award and the IEEE CAS Industrial Pioneer Award. In addition to his research, Rutenbar has been actively involved in education, launching MOOCs on chip design tools that have attracted over 60,000 learners globally. His work continues to influence both academic and industry practices in integrated circuit design and technology innovation.
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4.7 course rating
279 ratings
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