RISC-V CPU Core Development

Steve Hoover stands at the forefront of open-source silicon development as the founder of Redwood EDA, where he leads initiatives to democratize hardware design through innovative technologies. His significant contributions include developing the WARP-V CPU core generator supporting RISC-V architecture and pioneering Transaction-Level Verilog (TL-Verilog) methodology. As the lead developer of the first CLaaS open-source framework for cloud FPGAs, he has revolutionized access to FPGA technology. His academic credentials include a BS in Electrical Engineering (Summa Cum Laude) from Rensselaer Polytechnic Institute and an MS in Computer Science from the University of Illinois. His industry experience spans prestigious companies including DEC, Compaq, and Intel, where he designed critical components for high-performance server CPUs and network architectures. Through his work at Redwood EDA, he continues to advance the field of silicon design, making complex hardware development more accessible through open-source tools and methodologies. His innovative approaches to hardware design and commitment to open-source development have significantly influenced the evolution of silicon technology and FPGA accessibility.