Computer Architecture
Learn to design complex modern microprocessor architectures. Covers ISA, pipelining, caches, out-of-order execution, and multiprocessors.
Learn to design complex modern microprocessor architectures. Covers ISA, pipelining, caches, out-of-order execution, and multiprocessors.
This advanced course teaches the design of complex modern microprocessor architectures. It covers a wide range of topics in computer architecture, from fundamental concepts to cutting-edge techniques. The curriculum is structured into 21 modules, each focusing on different aspects of computer architecture. Key topics include instruction set architecture, pipelining, caches, superscalar processors, out-of-order execution, VLIW architectures, branch prediction, memory management, vector processors, GPUs, multithreading, and multiprocessor systems. Students will learn about the design trade-offs in modern processors, performance optimization techniques, and the challenges in scaling computer architecture. The course also covers parallel programming concepts and memory consistency models. Through a combination of video lectures, readings, and problem sets, students gain a deep understanding of how modern processors are designed and optimized for performance.
4.7
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English
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What you'll learn
Understand the principles of instruction set architecture and microarchitecture design
Master the concepts of pipelining and hazard resolution in processor design
Explore advanced techniques in superscalar and out-of-order execution
Learn about VLIW architectures and their compiler optimizations
Understand cache design and advanced cache optimization techniques
Explore branch prediction strategies and their impact on performance
Skills you'll gain
This course includes:
33.4 Hours PreRecorded video
2 assignments
Access on Mobile, Tablet, Desktop
FullTime access
Shareable certificate
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There are 21 modules in this course
This comprehensive course on Computer Architecture, offered by Princeton University, provides an in-depth exploration of modern microprocessor design. Over 21 modules, students will delve into the intricacies of computer architecture, from basic concepts to advanced techniques used in state-of-the-art processors. The course begins with fundamental topics such as instruction set architecture and pipelining, then progresses to more complex subjects including superscalar and out-of-order execution, VLIW architectures, and advanced caching techniques. Later modules cover crucial topics in modern computing, such as branch prediction, memory management, vector processors, and GPU architectures. The curriculum also addresses parallel computing concepts, including multithreading and multiprocessor systems, along with the challenges of parallel programming and memory consistency. Throughout the course, students will engage with theoretical concepts and practical design considerations, gaining insights into the trade-offs and optimizations necessary in high-performance processor design.
Introduction, Instruction Set Architecture, and Microcode
Module 1 · 3 Hours to complete
Pipelining Review
Module 2 · 3 Hours to complete
Cache Review
Module 3 · 2 Hours to complete
Superscalar 1
Module 4 · 2 Hours to complete
Superscalar 2 & Exceptions
Module 5 · 2 Hours to complete
Superscalar 3
Module 6 · 1 Hours to complete
Superscalar 4
Module 7 · 1 Hours to complete
VLIW 1
Module 8 · 1 Hours to complete
VLIW2
Module 9 · 2 Hours to complete
Branch Prediction
Module 10 · 2 Hours to complete
Advanced Caches 1
Module 11 · 2 Hours to complete
Advanced Caches 2
Module 12 · 2 Hours to complete
Memory Protection
Module 13 · 2 Hours to complete
Vector Processors and GPUs
Module 14 · 2 Hours to complete
Multithreading
Module 15 · 2 Hours to complete
Parallel Programming 1
Module 16 · 1 Hours to complete
Parallel Programming 2
Module 17 · 1 Hours to complete
Small Multiprocessors
Module 18 · 2 Hours to complete
Multiprocessor Interconnect 1
Module 19 · 2 Hours to complete
Multiprocessor Interconnect 2
Module 20 · 3 Hours to complete
Large Multiprocessors (Directory Protocols)
Module 21 · 2 Hours to complete
Fee Structure
Instructor
Innovator in Multicore Processor Design at Princeton University.
David Wentzlaff is an Associate Professor of Electrical Engineering at Princeton University. He earned his Ph.D. from MIT, where he also co-founded Tilera Corporation, serving as Lead Architect for the TILE64 and TILEPro64 processors and designing the scalable TILE processor architecture. Prior to his work at Tilera, he contributed to the design of the Raw Processor and its on-chip networks at MIT. Wentzlaff founded the MIT Factored Operating System (fos) project, focusing on scalable operating systems for thousand-core multicores and cloud computers. He holds a Master of Science in Electrical Engineering and Computer Science (EECS) from MIT and a Bachelor of Science in Electrical Engineering from the University of Illinois at Urbana-Champaign (UIUC). His current research interests include developing next-generation manycore processors for data centers and sustainable computing. Outside of academia, he enjoys hiking and mountaineering.
Testimonials
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4.7 course rating
2,922 ratings
Frequently asked questions
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